Explore BrainMass

Explore BrainMass

    Electrical Engineering

    Analysis of discrete time waveforms in z domain

    A discrete time domain signal x(n) - u(n) - u(n-10) is decomposed and plotted. It is then examined in the z domian by appropriate transformation and algebraic manipulation. From the z transform representation the poles and zeros are determined and plotted in the z domain

    From a given z transform X(z) = {1- z^-10}/{1 - z^-1} the discrete time domain form x(n) is deduced using complex manipulation and inverse transforms to arrive at x(n) = x(n-1) + u(n) - u(n-10) The second part shows how to convert the given X(z) into a polynomial in z as X(z) = 1 + z^-1 + z^-2 + .... + z^-9 Finally the third part goes on to show the poles and zeros of X(z) and plot these in the complex z plane as zeros , z(n) = 0.2n*pi, magnitude 1, Poles at 0

    From a given z transform X(z) = {1- z^-10}/{1 - z^-1} the discrete time domain form x(n) is deduced using complex manipulation and inverse transforms to arrive at x(n) = x(n-1) + u(n) - u(n-10) The second part shows how to convert the given X(z) into a polynomial in z as X(z) = 1 + z^-1 + z^-2 + .... + z^-9 Finally the th

    Mapping of Poles Into Complex Z and W (Laplace) Planes

    Given poles(in complex notation) are mapped to both the z and s (Laplace) planes. The transforms between the different planes are developed and the mappings grpahically shown for a number of examples. See the attached file.

    Safety, and Reliability Concerns and Risk

    1(a) Are safety and reliability concerns more or less important in an embedded application when compared to a non-embedded system? Why or why not? 1(b) What is risk? Give several examples of low and high risk embedded applications. Identify several embedded applications that may either be high or low risk depending on their o

    Digital Circuits in Counters

    a) A 4 bit binary up/down counter is set to zero. if the down mode is selected and five clock pulse applied, the counter value will be? b) A production plant has a requirement for a counter that will count 4,000 times before recycling and starting over. How many flip flpos are required?

    Pseudo Code

    Write the pseudocode for a program that does the following: The user is prompted to enter an integer between 1 and 1000. When the user enters the integer, the program uses a repetition control structure to validate whether the integer is within the proper range; otherwise, the prompt is continuously redisplayed to the user un

    Sampling rate, Systems function, Region of convergence

    ** Please see the attached file for the complete problem description ** 1. If the -3dB cut-off point for the filter shown (in the attachment) occurs for a real frequency of 200Hz then what should be the sampling rate (samples per sec)? 2. The difference equation for a digital filter is given by: y(n) = 2y(n-1) + y(n-2) + x

    Bode magnitude plot

    Please provide a step-by-step solution showing all the working. 1. Which of the following systems has the bode magnitude plot shown below? 2. Which of the following systems has the unit step response shown below? 3. Which of the following systems has the bode plot shown below? Please see the attachment for the respec

    Methods used to eliminate noise from a spatio-temporal signal

    Name and describe, in detail, 2 methods used to eliminate noise from a (spatio-temporal) signal. This question requires a clear, detailed explanation of the methods. Mathematical equations can/should be minimized. The application under consideration are signals from an EEG or MEG reading.

    S-R flipflops have a forbidden state that makes them hard to use.

    S-R flipflops have a forbidden state that makes them hard to use. Some designers switched to the following flipflop instead. Fill in the timing diagram shown. Then, describe what the flipflop does in each of the cases of M and N (i.e explain what the output does for each combination of the inputs). Note that filling in this timi

    This is a Java application that prints out numbers.

    Write a Java application that prints out numbers 2, 4 and 6 in row 1, numbers 3, 5 and 7 in row 2, numbers 8, 10 and 12 in row 3 and numbers 9, 11 and 13 in row 4. There should be an underline followed by a row of numbers that adds the numbers in the respective columns. The program should print out the information as follows:

    Three Fourier analysis of systems problems

    Fourier Analysis of Systems: 1. A linear time-invariant continuous-time system has the frequency response function H(Ï?)=5cos(2Ï?), compute the system's impulse response h(t): 2. A signal with the highest frequency component at 10 kHz is to be sampled. To reconstruct the signal, the sampling must be done at a minimum f

    System analysis and design

    Elmwood College Situation: The school is considering a new system that will speed up the registration process. As a systems analyst, you are asked to develop a plan for fact-finding. a. List all the possible techniques that you might use. b. Describe an advantage for each technique. c. Suppose the development budget is t

    Transfer Functions of Simple Filters

    Recall that the general formula H(w) = Vout(w) / Vin(w) can be used in several ways: for example, from the known transfer function and the output, you can calculate the input signal of the circuit. Part 1. In the circuit shown in the diagram, R = 1 kOhm and C = 50 nF; at 10 kHz, the output signal amplitude equals Vout = 5 Vp

    Design of a PD controller for a double integrator system

    The block diagram of a control system is given in the attachment.The inner loop is positive feedback, i.e. Ks>0, and hence the system is unstable. Adding a P-D controller on the forward channel and a unity negative feedback, one can stabilize the system. Find: 1. The conditions of Kc and Tc to stabilize the system. 2. T

    Impulse response using inverse discrete-time Fourier transform.

    An ideal low-pass filter is described in the frequency-domain by H_d(e^(jw)) = 1 . e^(-jaw) , |w| <= w_c 0 , w_c < |w| <= PI where w_c is called the cutoff frequency and a (denoting symbol alpha) is called the phase delay. Determine the ideal impulse response h_d(n) using the

    CMRR, RC-lag circuit, Bode plot, Open-loop midrange gain

    4. A certain op-amp has an open-loop voltage gain of 100,000 and a common mode gain of 0.2. Determine the CMRR in dB. 5. Find the open loop gain and phase shift for an RC-lag circuit at the following frequencies: (i) 1 Hz (ii) 10 Hz (iii) 100 Hz (iv) 1000 Hz (v) 10000 Hz. Plot the curve of phase shift versus frequency curve i

    Electrical Engineering: Op-Amp

    1. Show that gain rolls-off at -6 dB/octave for a passive LP filter. 2. (a) Write down the expression for the frequency-dependent open-loop gain of an operational amplifier. Sketch the magnitude of the open-loop gain of an operational amplifier as a function of frequency. Explain what is meant by a `single-lag' response of an

    Design a synchronous counter using J-K flip-flops

    Design a synchronous counter using J-K flip-flops that will count from 0010 to 1101 repetitively. a) Construct the "present state - next state" truth table. b) Complete the required K-maps for the design. c) Derive the minimised Boolean expressions for the J-K inputs. d) Draw the logic diagram for the counter.

    Slew rate, CMRR, Bandwidth, Critical frequency, Closed-loop gain

    Please refer to the attachment for the figures mentioned in these questions. 1. When a pulse is applied to an op-amp, the output goes from -40 V to +5 V in 0.6 microseconds. What is the slew rate? 2. A certain diff-amp (differential amplifier) has a differential voltage gain of 1500 and a common-mode gain of 0.5. Determine

    Block diagram and equations for control system water fill

    Develop a control system to fill a container with water after it is emptied through a stopcock at the bottom. The system must automatically shut off the water when the container is filled. Please show a block diagram explaining the operation of the developed control system.

    Gain of compensator, steady-state error and range of gain

    Please see the attachment for complete questions. 5. Find the gain (K) of the compensator so that overall closed-loop response to a unit step input has a maximum overshoot of 25%, and a 2% settling time of 0.1 sec. 7. Given the plant or process for a unity feedback system, find the steady state error for the given input.