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Electrical Engineering

Control signal processing problem

Consider the unity-feedback control system whose open-loop transfer function is G(s)= (as+1)/(s^2) Determine the value of a so that the phase margin is 45 degrees.

Shift Register and D FF's

- - - Draw a 3 bit shift register with a positive edge trigger D FF and an Enable signal. Have the date enter from the left and shit to the right, when enable is off nothing should happen. Then draw the output under D,clock,E conditions.

Inverse Nichols Chart

Question 4: a) Given P = [s/(-100) + 1]/[(s/4)^2 + 1.4(s/4) + 1], use the Inverse Nichols Chart to design a simple G(s) to achieve the following specifications. Show all design steps and sketch your final loop transfer function on the inverse Nichols Chart. i) Zero steady state error to a step output disturbance. ii) |1

System Modeles

Consider the system modeled by: x' = Ax + Bu , y = Cx + Du where dim x=2 and dim u = dim y = 1 a) Given u=0 and the initial-state responses 1 x(0) =  y(t) = e


Realize the following function using only two-input NAND gates. See attachment for function. I do not understand how i would get this with NAND gates? Please draw out so i can see.

Propagation Fundamentals- Cellular Systems

1. A cell is located over smooth, flat terrain. The system operates in the 1900 MHz band and the base station antenna is located 15 m above the ground. The mobile terminal is 250 m away from the base and its antenna is 1.5 m above the ground. (Use 1920 MHz in your computations.) (a) Compute the propagation loss. (b) What is

Micro Electric Circuits

For the depletion-load amplifier, let W1=80microm, L1=4micrometers, W2=8 micrometers and L2=32 micrometers. If the body-effect parameter X=0.2, find the voltage gain neglecting the effect on ro. a. -44.72 V/V b. -45.6V/V c. 44.72 V/V d. 45.6 V/V

Consider the system modeled by...

Consider the system modeled by: x' = Ax + Bu , y = Cx + Du -5 1 -1 A = , B = , C=[1 0] , D=0 1 -5 1 a) Determine the transition matrix eAt using the eigenvalues and eigenvectors m

Root Locus and Routh-Hurwitrz

I need some help solving this problem without matlab: a. Use Routh-Hurwitz to find vales of K so that L = k (s+1) / (s^2 +4) (s+10) has poles to the left of s= -2 b. Make a sketch of the root-locus of the above L(s) to explain the results above. You need to calculate the asymptotes (as s and k go to infinity) and angles of dep

Control System Specifications and Response

I need some help with this question, look at attached files for better symbol representation and also diagrams: For a system with P = (3e^-0.1x / 2s + 1), it is desired that a step input disturbance, di = 3 sigma (t), results in an output of not more than 0.1. (Note that the dead time gives a relatively small effect in the clo

Highpass Filter

Design a highpass filter with a cutoff frequency of 1000 Hz with a load resistance of 1000 ohms.

State space representation

Consider the following system whose state space representation is as follows: a) Assume that the initial conditions are zero. If the reference input is a unit step input , compute x1(t), x2(t), and y(t) b) Find the transfer function of the system. c) Using the transfer function found in (b), Compute y(t). d) Plot x1

Determine Simple Transfer Function

Assume that the operational amplifier is ideal; determine the transfer function V2/V1 of the circuit shown. See attached file for full problem description.

BJT Analysis

For the network of Fig. 8.82, determine RE and RB if Av = -10 and re = 3.8ohms. Assume that Zb = Bre Note: B = 120 ro = 80k ohm (See attached file for full problem description)

Systems Approach

*10. For the network of Fig. 10.53: (a) Determine AVNL, Zi and Zo. (b) Sketch the two-port model with the values determined in part (a). (c) Determine Av and Avs. (d) Change Rs to 1k and determine Av and Avs. What is the effect of increasing levels of Rs on the voltage gain? (e) Change Rs to 1k and determine Avnl, Zi, and

Pulse Generator

Using one 555 timer, design a pulse generator that will have the following continuously variable ranges: a) 0.1 kHz to 1kHz b) 1kHz to 10kHz c) 10kHz to 100kHz A duty cycle of 0.5 is required. Use the same potentiometer for all the 3 ranges.

Voltage divider

We want to design a voltage divider circuit to provide an output voltage Vo=5V from a 12V source as shown in the attachment problem, the current taken from the 12 V source is to be 100mA. Find values of R1 and R2.

LCR circuit

Find the particular solution for V(t) including the numerical values of all parameters. See attached

First order RC circuit

The switch opens at t=0. Find an expression for V(t) and sketch to scale versus time. See attached

Spectrum Limitations

(See attached file for full problem description) --- A signal x(t) of finite energy is applied to a square-law device whose output y(t) is given by y(t) = x2(t) The spectrum of x(t) is limited to the frequency interval -W ≤ f ≤ W. Show that the spectrum of y(t) is limited to -2W ≤ f ≤ 2W. (Hi


What percentage of modulation corresponds to a modulation index m of 0.5?

Capacitor and electric automobile

We want to store sufficient energy in a .01-F capacitor to supply 5-hp for 1 hour. To what voltage must the capacitor be charged? (1 hp=745.7 watts). Does this seem to be a practical method for storing this amount of energy? Do you think that an electric automobile based on capacitive energy storage is feasible?

''AND'' / ''OR'' GATES

Three two-input "AND" gates have their outputs connected to an "OR" gate. The first "AND" gate has each of its inputs at logic HIGH level. The second "AND" gate has each of it's inputs at logic LOW level. The third "AND" gate has one input at logic HIGH level, and the other input at logic LOW level. What is the output of the "OR

Systems & simulation analysis using Simulink

The cart in figure 1 rests on a ramp which is inclined 30 degrees with respect to the horizontal. At t=0s the cart is released from rest(i.e with no initial velocity). As indicated, the air resistance is proportional to the velocity squared. See attached

J-K Flip-flops

Using negative edge triggered J-K flip-flops, design a 3-bit synchronous sequence generator to generate the following sequence: 0,1,3,6,0..... 1. Draw up a table showing the input requirements on the J & K terminals for the four possible changes of state at the output. The table should be headed: PRESENT Q, NEXT Q, INPUTS J