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6.5 A half adder is a combinational logic circuit that has two inputs, x and y, and two outputs, s and c, that are the sum and carry-out, respectively, resulting from the binary addition of x and y.

(a) Design a half adder as a two-level AND-OR circuit.
(b) Show how to implement a full adder, as shown in Figure 6.2a, by using two half adders and external logic gates, as necessary.
(c) Compare the longest logic delay path through the network derived in Part (b) to that of the logic delay of the adder network shown in Figure 6.2a.

Figure 6.2a
Part b

6.6 Write a 68000 or IA-32 program to transform a 16-bit positive binary number into a
5-digit decimal number in which each digit of the number is coded in the binary-coded decimal (BCD) code. These BCD digit codes are to occupy the low-order 4 bits of are special five successive byte locations in the main memory. Use the conversion technique based on successive division by 10. This method is analogous to successive division by 2 when converting decimal-to-binary.

6.8 A modulo 10 adder is needed for adding BCD digits. Modulo 10 addition of two BCD digits, A = A3A2A1A0 and B = B3B2B1B0, can be achieved as follows: Add A to B (binary addition). Then, if the result is an illegal code that is greater than or equal to 1010, add 610. (Ignore overflow from this addition.)

(a) When is the output carry equal to 1?

(b) Show that this algorithm gives correct results for

(1) A =0101 and B =0110

(2) A = 0011 and B = 0100

(c) Design a BCD digit adder using a 4-bit binary adder and external logic gates as needed. The inputs are A3A2A1A0, B3B2B1 B0, and a carry-in. The outputs are the sum digit S3 S2 S1 S0 and the carry-out. A cascade of such blocks can form a ripple-carry BCD adder.

(a) Design a 64-bit adder that uses four of the 16-bit carry-look-ahead adders shown
them in all in Figure 6.5 along with additional logic to generate c16, c32, c48, and c64, from co and the G11i and P11i variables shown in this figure. What is the relationship of the additional logic to the logic inside each look-ahead circuit in the figure?

(b) Show that the delay through the 64-bit adder is 12 gate delays for s63 and 7 gate delays for c64.

(c) Compare the gate delays to produce s31 and c32 in the 64-bit adder of part (a) to the gate delays for the same variables in the 32-bit adder built from a cascade of two
16-bit adders.
Figure 6.5

(a) How many logic gates are needed to build the 4-bit carry-look-ahead adder shown in Figure 6.4?

(b) Use appropriate parts of the result from Part (a) to calculate how many logic gates Part (b) to be needed to build the 16-bit carry-look-ahead adder shown in Figure 6.5.

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