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Direct-mapped cache, Fully-associative cache

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1. A computer using direct-mapped cache has 2^24 words of main memory and a cache of 256 blocks. Each cache block contains 64 words.

a) How many blocks of main memory are there?
b) What is the format of a memory address as seen by the cache? (What are the sizes of the tag, block and word fields?)
c) To which block will the memory reference 01BD36 (in hexadecimal) map?

2. A computer using fully-associative cache has 2^32 words of main memory and a cache of 1024 blocks. Each cache block contains 32 words.

a) How many blocks of main memory are there?
b) What is the format of a memory address as seen by the cache? (What are the sizes of the tag, block and word fields?)
c) To which block will the memory reference 025A13CF (in hexadecimal) map?

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Solution Preview

1. Size of main memory (Sm) = 2^24 words
Size of direct-mapped cache (Nb) = 256 blocks or 2^8 blocks
Size of a cache block (Scb) = 64 words or 2^6 words

(a) So, total number of blocks of main memory = Sm / Scb = 2^24 / 2^6 = 2^18 blocks

(b) From the given information,
size of word field = 6 bits
size of block field = 8 bits
size of tag field = 24 - 8 - 6 = 10 bits

So, the format of a memory address as seen by the cache will be ...

Solution Summary

In fully-associative cache it is one big set comprising of all the cache blocks. To which cache block will a memory block map to, can not be determined unless ... .

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See Also This Related BrainMass Solution

Which bits would be used for tag, index, and offset in address reference? What is the expected access time for the following cache configuration? Additional Primary or Secondary cache could be added at same cost - which would be the better addition?

1. Answer the following questions related to reference addresses:

a. Given a 64-byte cache block, a 4 KB direct-mapped cache (assume byte-addressable), and a 32 bit address reference, which bits would be used for tag, index, and offset?

b. Given a 64-byte cache block, a 32 KB direct-mapped cache (assume byte-addressable) and a 32 bit address reference, which bits would be used for tag, index, and offset?

c. Given a 64-byte cache block, a 512 KB fully associative cache (assume byte-addressable), and a 32 bit address reference, which bits would be used for tag, index, and offset?

d. Given a 128-byte cache block a 2 MB 8-way set associative cache (assume byte-addressable, and a 64 bit address reference, which bits would be used for tag, index, and offset (note that `way' denotes the number of blocks)?

2. Answer the following questions:

a. What is the expected access time for the following cache configuration: Primary Cache: access time, 1 cycle; hit ratio, 80% Secondary Cache: access time, 10 cycles; hit ratio, 96% Memory: access time, 100 cycles.

b. Additional Primary or Secondary cache could be added at same cost. If additional primary cache results in a 92% hit rate and additional secondary cache results in 97% hit rate, which would be the better addition?

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