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Cache: Expected access time, Address reference format

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1. Answer the following questions related to reference addresses:

a. Given a 64-byte cache block, a 4 KB direct-mapped cache (assume byte-addressable), and a 32 bit address reference, which bits would be used for tag, index, and offset?

b. Given a 64-byte cache block, a 32 KB direct-mapped cache (assume byte-addressable) and a 32 bit address reference, which bits would be used for tag, index, and offset?

c. Given a 64-byte cache block, a 512 KB fully associative cache (assume byte-addressable), and a 32 bit address reference, which bits would be used for tag, index, and offset?

d. Given a 128-byte cache block a 2 MB 8-way set associative cache (assume byte-addressable, and a 64 bit address reference, which bits would be used for tag, index, and offset (note that `way' denotes the number of blocks)?

2. Answer the following questions:

a. What is the expected access time for the following cache configuration: Primary Cache: access time, 1 cycle; hit ratio, 80% Secondary Cache: access time, 10 cycles; hit ratio, 96% Memory: access time, 100 cycles.

b. Additional Primary or Secondary cache could be added at same cost. If additional primary cache results in a 92% hit rate and additional secondary cache results in 97% hit rate, which would be the better addition?

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Solution Summary

Step by step calculations are shown along with brief explanations and relevant formulas used.

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[1a]
Offset bits = lg(size of cache block in bytes) = lg(64) = 6 bits (bits 0:5)
Index bits = lg(size of direct-mapped cache in bytes) = lg(4 KB) = lg(4096) = 12 bits (bits 6:17)
Tag bits = 32 - 6 - 12 = 14 bits (bits 18:31)

Offset and index bits are subtracted from 32 because the address reference is 32 bits.

[1b]
Offset bits = lg(size of cache block in bytes) = lg(64) = 6 bits (bits 0:5)
Index bits = lg(size of direct-mapped cache in bytes) = lg(32 KB) = lg(32768) = 15 bits (bits 6:20)
Tag bits = 32 - 6 - 15 = 11 bits (bits 21:31).

Offset and index bits are subtracted from 32 because the address reference is 32 bits.

[1c]
In case of fully associative cache, address reference ...

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