(i) Under 2-way set associativity, to which blocks of cache may element 31 of memory go?
(ii) In the sequence of memory block references from the CPU [0,2,10,45,10,2,44,35,26,44,45,10], beginning from an empty cache, will layout for a direct mapped and a 4-way set associative cache differ? What will be the mappings between cache block number and memory block number in each case?
Memory of 64 blocks can be addressed using 6 bits address.
(i) Under 2-way set associative organization, the cache of 16 blocks will be organized in 8*2 format i.e. 8 sets of size 2 blocks each. Since each memory block has to be mapped to one unique set in this cache organization, we look at the lower 3 bits of the block's memory address, and use that to determine which cache set it will go in.
31 (decimal) = 011111 (binary)
Lower 3 bits in above address are 111, indicating that the memory block with above address will go to cache set number 7.
Assuming that the cache is currently empty, in that ...
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