I have attached a cmos library for various transistors that pspice does not currently have. I only have access to the Q2N2222 BJT, CD4007 MOS transistor and the 2n7000 transistor and of course all the various resistors and capacitors. If you could please help me design a circuit with the attached specifications using only the parts I have mentioned, and I am actually trying to build this circuit so it would be nice if the resistance values used in calculations were close to normal physical resistor values but is not necessary, I understand that they will not be exact. And any pieces that pspice does not currently support will be in the cmos library I attached. Just in case you need instruction on how to import them.
1. Download cmos.slb and cmos.lib, and store in your hard disk
(preferably, within C:Program FilesOrCAD_DemoPspiceUserLib).
Remove the index file cmos.ind if you have an earlier version.
2. From Pspice Schematics menu:
Choose Options -> Editor Configuration
Click on Library Settings
Click on Browse, find cmos.slb, and click on Open
Click on Add*
Click on OK, OK.
3. From Pspice Schematics menu:
Choose Analysis -> Library and Include Files
Click on Browse, find cmos.lib, and click on Open
Click on Add Library*
Click on OK.
Design a three-stage ampliﬁer with Bipolar and CMOS transistors to satisfy the following constraints.
Note. the design should use standard value resistors (no potentiometers).
- Av >= 0
- Ra 2 200 Kohm
- Harmonica distortion below -30dB with vi-. I $rnV¢. (l0mV,,)
- Vq: I tnlnlrnur required. but absolute mas-SV
- Ri-4 I 80. Note, you may have to use multiple transistors in parallel in the output stage to drive
this load. Check the power ratings of the transistors.
- Use a minimum of MOSFETs in your design. Note. if desired you cart use more and also
BITS. but the intent is the MOSFE'l's are a key part of your design.
describe the design procedure stage-by-stage. beginning with the output stage.
Provide sufficient theoretical and quantitative justification on the 'liq-3 choice. Try to optimize Vu-
on a per-stage basis to achieve the lowest power.
Needed PSPICE simulation results:
i DC operating points [voltages & currents} for each stage
- AC Plots ﬁ'om 1[lDHz to lt]IIIIkI-I2: Av, Rm
- Transient plot of output signal with input of a sine wave of 5n1V amplitude
¢ Frequency domain plot of above transient which shows the harmonic distortion. Note, to verify
the -3IIldB harmonic distortion spec, Idle harmonic distortion for a given harmonic is the ratio of
the harmonic power over the ﬁind a rnental power.
- Include the text output of the Fourier Analysis which states the Total Harmonic Distortion
- Total power dissipation
This posting contains the solution to the given problem.
Bias stable circuit design with capacitors
For the circuit, design a bias stable circuit such that Icq=.8mA and Vceq=5V. Let Bf=100. Using the results, determine the percentage change in Icq if Bf is in the range of 75<=Bf<=150. Repeat this if Re=1kOhms.
I can do KVL around the b-e loop to find Vth, but how do I split the two resisters out of Rth? Anything could be r1*r2/(r1+r2)
The capacitors are confusing me. If they act as opens, then RL is irrelevant? By the way, what is the function of the emitter capacitor? (just curious)
Is the part B, do you think the author means the difference between the upper value of Icb and the lower value of Icb? Or what percent of icblower is icb upper? It's a little confusing.
Thank you.View Full Posting Details