Two D-Type Flip-Flop Questions

Please help me solve the following problems.

Problem 1: Consider the following circuit (see attached).
IC 1 is a 3-bit asynchronous (ripple) counter, positive-edge triggered. At higher speeds propagation delay will affect the proper function of the counter so that the counting sequence is altered. Glitches will be produced and, as the clock speed is increased to the point where the first stage changes state at the same time as the last stage, the final count value will not be achieved. IC 2 is a 3-line to 8-line decoder/demultiplexer (e.g. 74ALS138). In this circuit the output Y2 goes low for an input of CBA = 010, and is high otherwise.

a. Draw a circuit to perform the function of IC 1 using D-type flip-flops. Test your design by drawing the waveform noting that the D-types are positively-edged triggered.
b. What is the maximum clock speed that the counter can operate at and still give the full range of valid counts where each count has a period of at least 50 nsecs. The delay per D-type stage is 20 nsecs. Explain your answer and illustrate by drawing the waveform to demonstrate the frequency at which there will be no zero count state.
c. If the input is clocked with a square wave of 10 MHz and IC1 has a propagation delay per stage of 20 nsecs, and IC2 also has a delay of 20 nsecs, draw a waveform diagram approximately to scale for the input clock and the outputs QA, QB, QC and Y2.
d. Comment on any problems with the above circuit, and how they might be overcome.

Problem 2: Using positive edge-triggered D-type bistables with clear and preset terminals design a 3-bit synchronous sequence generator to give the following continuous sequence: 4,2,5,6,3,1,4 ... ... ...
The sequence includes 6 non-zero states before it repeats
a. Draw a state table for the required sequence showing:
For each state change. Treat the states 000 and 111 as don't care states.
b. Use any method to derive minimized logic expressions for each D input.
c. What would the next state be, if, at switch-on, the 000 output state were to occur. Explain why this happens. Suggest how the design could be modified to overcome this.