# Seqeuntial circuits, analysis, truth tables and state diags

This solution shows how to work from a given circuit implementation (a J-K flip flop circuit design) to derive the Boolean Logic and in so doing so simplify such logic using Boolean Algebra rules. The solution then goes on to show how such next state logic can be applied to K maps (that describe the next states) and derives next state truth tables. Finally the solution shows how, from the next state truth table, the state diagram can be derived.

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#### Solution Preview

As there are truth tables and diagrams in the solution it is best to open up the attachment (word document) to see the full solution in all its glory with K maps, circuit diagrams and turth table/state diagrams included with the explanatory text.

Analysing clocked flip-flop type circuits using K Maps and Boolean Algebra, producing next state tables and diagrams

The diagram (Figure 1) below shows a sequential network consisting of 2 JK flip flops and inputs X,Y and with an output Z. With respect to this network answer the questions that follow

{SEE ATTACHMENT FIGURE 1}

Figure 1: Sequential circuit diagram consisting of 2 J-K flip flops.

(Q1) What type of general sequential network is this? Explain your answer?

(A1) This sequential network is a Mealy type network because the output Z is a function of input X and the present state B of the second flip flop.

i.e. Z = X.B

(Q2) Identify the flip flop input Boolean equations for both flip flops A & B

(A2) The flip flop input equations can be identified from the above schematic thus,

JA = X.B ......( 1 )

KA = Y ......( ...

#### Solution Summary

This shows a worked example to show how from working from an initial circuit diagram/description one can derive the next state logic, minimise that logic and produce next state descriptions using K maps. The next state K maps the state transition diagram is derived both for the specific case and the general case and this is then used to produce a state transition diagram describing the circuit function. A two module J-K flip flop design is provided as the starting circuit implementation and this is analysed in the context of the solution. A step by step approach is shown that eventually results in realisation of the sate diagram.