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# Boolean Algebra : Gates, Truth Tables and Logic Operations

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(See attached file for full problem description)

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For question #1, just use the example to show how to solve a problem like it is.

1. Gates Implement the 1 bit full adder using only:
1. 2 input NAND gates
2. 2 input NOR gates.

2. Boolean Functions
Using the laws of Boolean algebra, minimize the number of operators in the following Boolean functions:
1. wy'+ wx'y + wxyz + wxz'
2. abc + a'd + b'd + cd

3. Given the following truth table, write the Boolean function, simplified as much as possible. Draw the logic circuit using only 2-input AND, OR and NOT gates.
xwyz F
0000 0
0001 1
0010 0
0011 0
0100 0
0101 1
0110 0
0111 1
1000 0
1001 1
1010 1
1011 1
1100 0
1101 1
1110 1
1111 1

4. Logic Operations
Given A,B are 32 bits wide. Write the result stored in B after each one of this operations (for each line, assume B has the value assigned to it by the previous operation). Write your results using hexadecimal numbers. A = 0x12345678 (initial value)
1. B = A AND 0x87654321
2. B = B XOR 0x33333333
3. B=BORA
4. B=NOTB
5. Combinational Circuits
Design a binary-to-decimal decoder whose inputs are 4-bit BCD-encoded numbers (x3x2x1x0) and whose outputs are lines (d9, d8,. . . , d0). The circuit should be minimized as much as possible.

https://brainmass.com/math/boolean-algebra/boolean-algebra-gates-truth-tables-and-logic-operations-80719

#### Solution Summary

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## Voltage range at the input, 7-bit even parity logic

1. For the voltage conditions Z = 0.2 V when A = 0.65 V, and stating any assumptions, give the voltage range at the input B required to achieve the stated voltage conditions.

Z = A.b + a.B (Exclusive OR), where a,b respectively indicate A bar and B bar.

2. Implement a 7-bit even parity logic, and draw and label a diagram showing the connections among the gates used to implement this logic.

3. The block diagram, shown in Figure 2 (in the attachment), represents a 3-bit equivalence logic function in which the output Q is high when the inputs are equivalent (that is, when simultaneously A0=B0, A1=B1 and A2=B2).

Design and verify the equivalence function as follows:
a) For each input pair (Ai, Bi) draw a truth table to show intermediate output states (Qi) against the tabulated inputs; for example, a truth table for A0, B0 and Q0.
b) Hence, show that each intermediate output is the exclusive-NOR of the inputs.
c) Draw a truth table to show the output Q as a function of the intermediate states (Q0, Q1 and Q2).
d) Hence, show that the output (Q) is a 3-input AND function of the intermediate terms (Q0, Q1, Q2).
e) Draw and label a diagram showing the connections among the exclusive-NOR gates and the AND gate to implement the equivalence logic.

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