Algorithm Implementation of Edge Triggered
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(See attached file for full problem description)
1. S-R Latch
Given the following NAND implementation of an S-R latch,
Write its truth table.
Qt St Rt Qt+1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
2. Gate S-R latch.
Given the following implementation of a gated (clocked) S-R latch and its truth table.
S R C Q Q'
0 0 1 lastQ lastQ'
0 1 1 0 1
1 0 1 1 0
1 1 1 1 1
x x 0 lastQ lastQ'
Draw the Q output in the timing diagram:
** assume NO time delay for transitions
3. Gated D Latch.
Given the following implementation of a gated D latch and its truth table.
CD Q Q'
10 0 1
11 1 0
0 x lastQ lastQ'
Draw the Q output in the timing diagram:
** assume NO time delay for transitions
4. Edge triggered D Flip Flop
Given the following implementation of an edge triggered D flip flop and its truth table.
D Q
0 0
1 1
Draw the Q output in the timing diagram:
** assume NO time delay for transitions
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Solution Summary
The implementation of an edge triggered D flip flop and its truth tables are determined. The output in the timing diagrams are discussed.
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