Adder implementation for NAND Gate
Not what you're looking for? Search our solutions OR ask your own Custom question.
This content was COPIED from BrainMass.com - View the original, and get the already-completed solution here!
We've said that NANDs (or NORs) only may be used to implement any combination of the 7 basic Boolean logic units which, in turn, may be used to construct circuits to do base 2 arithmetic. Shown below is an implementation of a full-adder using 9 NAND gaes. Each NAND can be made using 2 NMOS and 2 PMOS transistors, for a total of 36 MOSFETS to obtain the 2-digit full-adder.
(See attached file for full problem description)© BrainMass Inc. brainmass.com March 6, 2023, 2:16 pm ad1c9bdddf
This solution provides an analysis for a question involving NAND only implementation of a full-adder.