1. Using Multisim, design a mod-100 BCD counter that drives a 2-digit, 7-segment display. The count sequence will be 0 through 99. Blank leading zeros in the tens digit of the display.
2. Design an octal-to-binary switch encoder and 7-segment display circuit using a 74148 priority encoder, a 7447 decoder/driver chip, and any other necessary devices. The display should be blanked when there is no switch input being applied. Use pushbutton switches to change the output on the display. Use the 7 segment display indicator to visually verify the circuit operation.
3. Design a 16-channel, 1-bit multiplexer using AHDL. Label the inputs d[15..0] and sel[3..0] and the output y. Compile and simulate your results. For the simulation, let sel[3..0]=9 and place a 1kHz square wave on d9 of d[15..0]. Make sure you see the square wave at the output y. Kindly give the AHDL file (.tdf) and waveform simulation (.vwf) file.
4. Using AHDL, design a logic circuit that will compare a 5-bit value (value[4..0]) to one of four specified input ranges by the control r[1..0]. The comparator should have three outputs to indicate that the input value is either less than (ltr) or greater than (gtr) the range of values in the selected window or with the range (rng) of window values.
R1 R0 Selected range of window values
0 0 16
0 1 15-17
1 0 14-18
1 1 13-19
Compile and simulate your results. Give both AHDL and simulation results.© BrainMass Inc. brainmass.com October 25, 2018, 3:11 am ad1c9bdddf
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Wireless Networks - Encoder Output
1) The figure attached shows the encoder for a ½ rate convolution code. Determine the encoder output produced by the message sequence 1011. Assume that the initial state of the encoder is zero.
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