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RISC machine assembly: delayed branching

Consider the following loop:

S:= 0;
for K := 1 to 100 do
S : = S - K;

A straightforward translation of this into a generic assembly language would look something like this:

LD R1,0 ;KEEP VALUE OF S IN R1
LD R2,1 ;KEEP VALUE OF K IN R2
LP SUB R1,R1,R2 ;S := S - K
BEQ R2,100,EXIST ;DONE IF K = 100
ADD R2,R2,1 ;ELSE INCREMENT K
JMP LP ;BACK TO START OF LOOP

A compiler for a RISC machine will introduce delay slots into this code so that the processor can employ the delayed branch mechanism. The JMP instruction is easy to deal with, because this instruction is always followed by the SUB instruction; therefore we can simply place a copy of the SUB instruction in the delay slot after the JMP; The BEQ presents a difficulty. We can't leave the code as is, because the ADD instruction would then be executed one too many times. Therefore, a NOP instruction is needed. Show the resulting code.

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Resulting code will look like following.

LD R1,0 ;KEEP VALUE OF S IN ...

Solution Summary

RISC machine assembly for delayed branching is examined.

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