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Karnaugh Map reduction for D Type Asynchronous counter design

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Q4 A three-stage type D counter circuit is required to produce the waveforms below (see Question4 attachment).

A skeletal form of the counter circuit is given in the PSpice schematic* (Question4PSpiceschematic attachment), along with the associated truth table (Question4TruthTable attachment). The outputs of the circuit are A, B and C and they are generated by the counter outputs Q1, Q2 and Q3.

a) Derive the relationship [a Boolean expression] between each output and the inputs [by, for example, plotting a Karnaugh map for each output].

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Karnaugh Map Boolean logic reduction is used to derive minimized logic for an Asynchronous Counter built from D Type Flip Flops

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I have drawn a Karnaugh map for output A. Note when drawing Karnaugh Maps you need to make sure that you label adjacent cells so that they only differ in changing one digit at a time, so for instance if you look at the vertical column axis for D1D2 it is labelled 00, 01, 11, 10 (note each cell in this sequence ...

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