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Microprocessor Combinational Logic

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Discussion Forum: Combinational Logic, Storage Elements and Finite State Machines

? What are the consequences of increasing the rise time of a logic signal? The fall time?
? The state of the system can convey important information about a system. Can you think of situations in which the state of a system can be a problem? Consider cases in which the system has failed and is recovering.

Discussion Forum: Memories & the Memory Subsystem and Intro to Software Modeling

? Discuss the pros and cons of static and dynamic allocation of memory in embedded applications. Be certain to address the circumstances under which there may be potential problems.
? When designing the software for a multitasking embedded system, why is the understanding of and the ability to model concurrency important?

Discussion Forum: The C Program, Pointers and Functions

? Why would we wish to qualify a variable that is being passed into a function as const? Please provide a specific example of when such a practice might be particularly useful in an embedded application.
? Discuss the advantages and disadvantages of using pass by reference versus pass by value in an embedded C program.

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Discussion Forum: Combinational Logic, Storage Elements and Finite State Machines

? What are the consequences of increasing the rise time of a logic signal? The fall time?

Ans: The rise time and fall time of a digital logic signal describe the slew rate requirement for a logic circuit to which it is fed. This means the rate of change of its output [from high to low, or from low to high]. Or the amount of time it takes an IC to switch from 10% to 90% of its final value in a given time. Slow rise times are usually considered to be longer then 50nS. Typical rise and fall times for most logic devices range from between 1nS and 4nS.

? The state of the system can convey important information about a system. Can you think of situations in which the state of a system can be a problem? Consider cases in which the system has failed and is recovering.

Ans: In case of failure, system state may have erroneous values which can result in unreliable outputs if left unchecked. Digital fragility can be reduced by designing a digital system for robustness e.g. a parity bit or other error management method can be inserted into the signal path which help the system detect errors, and then either correct the errors, or at least ask for a replica of information from the source system. In most of the cases some state transition logic is designed to catch unused states and trigger a reset sequence or other error recovery routine.

Discussion Forum: Memories & the Memory Subsystem and Intro to Software Modeling

? Discuss the pros and cons of static and dynamic allocation ...

Solution Summary

The expert examines microprocessor combinational logic. The pros and cons of static and dynamic allocation of memory in embedded applications are determined.

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