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Adder implementation for NAND Gate

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We've said that NANDs (or NORs) only may be used to implement any combination of the 7 basic Boolean logic units which, in turn, may be used to construct circuits to do base 2 arithmetic. Shown below is an implementation of a full-adder using 9 NAND gaes. Each NAND can be made using 2 NMOS and 2 PMOS transistors, for a total of 36 MOSFETS to obtain the 2-digit full-adder.

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This solution provides an analysis for a question involving NAND only implementation of a full-adder.

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